Sandy Bridge Information

Sandy-Bridge chipsets (e.g: QM67 Express):
The Intel Sandy-Bridge chipset contains a bug.
The BIOS typically introduced a workaround that claims two physical memory areas are not available. If this workaround is active, the following memory areas in "HKEY_LOCAL_MACHINE\HARDWARE\RESOURCEMAP\System Resources\Loader Reserved" and "HKEY_LOCAL_MACHINE\HARDWARE\RESOURCEMAP\System Resources\Reserved" are visible:
- Start 512MB, Length 2MB
- Start 1024MB, Length 2MB

As a consequence, these areas cannot be used by the real-time part (e.g. at the base address 64MB a maximum of 448MB (=512MB-64MB) can be used.

Example: Adjustment of the VxWin Memory Settings

The base address of the real-time part has to be set to 1028 MByte (behind the Sandy Bridge Memory hole). How to configure the memory of the Windows part of VxWin is described in the RtosVM-UserManual.pdf. For example in section 4.3.
The following parameters shall be adjusted: RteMemoryStartAddress and MemoryStartAddress should be identical (1028 MB = dword:40400000) RteMemorySize should be at least the same as MemorySize. It depends on the customer's requirements.

The VxWorks image has to be linked to the same address.
The VxWin BSP has to be adjusted accordingly:
RAM_LOW_ADRS = 40400000
#define LOCAL_MEM_LOCAL_ADRS 0x40400000 /* VxWorks memory base */
#define RAM_LOW_ADRS 0x40408000 /* VxWorks image entry point */
If Wind River Workbench is used, the settings also have to be adjusted (LOCAL_MEM_LOCAL_ADRS, RAM_LOW_ADRS).