Intel Chipset Cache Architecture Information
On this page we want to show the architecture and function of Intel Chipsets and why there could be some real-time issues.
Since Intel has the GPU the function is as you can see in the following picture:
More Information: the-architecture-of-intel-processor-graphics-gen11-r1new-810410.pdf
Please note, the BIOS is responsible for managing how the L3 cache is shared with the CPU (see section 7.3 GT COS). You may have to check with your BIOS vendor if TCC is enabled.